Senior Staff Engineer, Design Verification (Power & Analog ICs)

Renesas is a global semiconductor leader shaping the backbone of next-generation automotive, industrial, cloud, and IoT innovation.

With over $9.3 billion in annual revenue (2024) and a world-class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category-defining breakthroughs.

The company's footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovation engine.

As Japan's semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real-world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence.  Renesas has a growing presence in India with headcount approaching 1000+ and significant engagement with government, universities, and the semiconductor manufacturing ecosystem.

With the growing importance of India as both a market and talent hub, the India for India division's mission is to create products, including power and analog ICs, mixed-signal devices, software, and system solutions, that address local market needs.

This is a unique opportunity to directly influence future products for a fast-growing Indian market with distinct applications, cost structures, and localization requirements.  We are seeking a Senior Staff Design Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products.

This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level.  The successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry.  You will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out.  Responsibilities   Verification Strategy & Ownership  Own block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products.  Develop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria.  Decompose complex functions into reusable verification components and scalable environments.  Identify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams.  Environment Development & Execution  Design and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models.  Set up verification flows from scratch where needed and own regression execution, triage, debug, and closure.  Apply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value.  Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.  Mixed-Signal, DFT & Post-layout Support  Collaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level.  Support DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification.  Support gate-level simulation, timing-aware verification, and post-layout verification where required.  Contrib