Senior Staff Engineer, Layout Design (Power & Analog ICs)

Renesas is a global semiconductor leader shaping the backbone of next-generation automotive, industrial, cloud, and IoT innovation.

With over $9.3 billion in annual revenue (2024) and a world-class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category-defining breakthroughs.

The company's footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovation engine.

As Japan's semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real-world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence.  Renesas has a growing presence in India with headcount approaching 1000+ and significant engagement with government, universities, and the semiconductor manufacturing ecosystem.

With the growing importance of India as both a market and talent hub, the India for India division's mission is to create products, including power and analog ICs, mixed-signal devices, software, and system solutions, that address local market needs.

This is a unique opportunity to directly influence future products for a fast-growing Indian market with distinct applications, cost structures, and localization requirements.  We are seeking a Senior Staff Layout Design Engineer with deep expertise in analog and mixed-signal layout for power and analog IC products.

This is a senior individual-contributor role requiring strong technical ownership, independent judgment, and the ability to lead layout execution for complex blocks and full-chip designs.  The successful candidate will translate circuit requirements into robust, manufacturable layouts for products such as PMICs, linear and switching regulators, gate drivers, battery-management ICs, and other power and analog devices.

The role requires close collaboration with analog designers, CAD, process, package, reliability, and verification teams.  You will be expected to own challenging layout problems, establish best practices, improve methodology and automation, mentor engineers, and drive projects from floor planning through physical verification and tape-out readiness.  Responsibilities Layout Architecture & Execution  Own floor planning and physical implementation for complex analog, power, and mixed-signal blocks, and contribute to full-chip layout planning.  Collaborate with circuit designers to capture electrical, matching, isolation, current-density, thermal, reliability, and area requirements.  Apply advanced layout techniques for device matching, parasitic reduction, noise isolation, high-current routing, electromigration robustness, thermal behavior, and yield optimization.  Drive routing, integration, and sign-off readiness for block-level and chip-level layouts.  Physical Verification & Sign-off  Own and review DRC, LVS, ERC, PEX, antenna, density, latch-up, and reliability verification as required by the process and product.  Analyse extracted parasitics with designers and support post-layout simulation closure.  Identify physical-design risks early and drive corrective actions with design, CAD, PDK, process, and package teams.  Ensure layout databases, review records, and release documentation meet tape-out quality standards.  Methodology, Automation & IP Reuse  Develop and deploy automation using SKILL, TCL, Python, Perl, or similar languages to improve quality and turnaround time.  Drive layout methodology improvements, reusable templates, checklists, and portability of IP across products and process technologies.  Work with corporate engineering and CAD teams to resolve tool, PDK, extraction, and process-flow issues.  Evaluate new layout tools and t